Coherency Verification engineer

Coherency Verification Engineer

We are looking for a Coherency Verification Engineer to join an experienced verification team focused on validating complex digital designs. In this role, you will contribute to the verification of microprocessor architectures at Register Transfer Level (RTL), ensuring design correctness through advanced verification methodologies and industry-standard tools.

Responsibilities

• Develop and execute verification plans for complex RTL digital designs.

• Verify coherency functionality using SystemVerilog and UVM methodologies.

• Create and maintain verification environments, testbenches, and regression flows.

• Perform block-level, subsystem-level, and top-level verification activities.

• Collaborate with engineering teams to identify, analyze, and resolve design issues.

• Apply formal and dynamic verification techniques to validate design specifications.

Requirements

• Master's degree or PhD.

• More than 8 years of industrial experience in verification.

• Proficiency in SystemVerilog, UVM, scripting languages (Python, Perl, Bash, TCL), and regression tools.

• Experience with simulation tools, Git or SVN, and block, subsystem, or top-level verification.

• Knowledge of the CHI protocol, cache structures, and verification of coherent systems.

• Strong problem-solving skills, attention to detail, excellent communication abilities, and English level C1.

Benefits

• Salary range: Up to 80k

• Hybrid working model (Barcelona city centre, specifically 4 days per week at the office).

• Flexible working schedule.

• Highly collaborative environment with real opportunities for professional growth.

• Visa sponsorship (if required).

If you believe you are the ideal candidate for the Coherency Verification Engineer role, do not hesitate to apply to the offer with your LinkedIn profile or uploading your CV.

We will contact you very soon!

Truthfully, your People Partner